|
|
The Buttons on the Logic Analyzer Hardware Own the Function of Sampling: |
| |
There is a START button on the hardware of the Zeroplus Logic Analyzer, and pressing this button can make the Logic Analyzer sample signals when the software of Logic Analyzer is activated. Users can quickly capture data from the testing board by using the START button. |
| |
|
|
|
Compression |
| |
| |
Zeroplus Technology issues the patent technology of Waveform Compression which can capture more waveform data without adding the size of the RAM.
For example: The RAM Size is set as 1M, and the Sampling Frequency is set as 50MHz. When the Compression function is not activated, Zeroplus Logic Analyzer can only capture waveform data within 20.972ms; when the Compression function is activated, with the same RAM Size (1M) and Sampling Frequency (50MHz), the Logic Analyzer can prolong the waveform data to 3.999s. That is to say, the function of Waveform Compression can improve the amount of the captive data largely. |
| |
|
|
|
Signal Filter Delay |
| |
| |
Zeroplus Technology issues the patent technology of Signal Filter Delay. The function of the Signal Filter Delay can capture the signals conditionally. For example, the Filter Condition of channel A1 is set as High Level; the differences can be seen obviously by the horizontal windows, and the Filter Delay Setup can make the conditions of the Signal Filter more flexible; users can set the time of the Filter Delay as their requirements.
For example: Clients found Bugs in a group of DUT. The content of the Bug is that a read error may be presented while the program tries to read the data. At that moment, users can use the function of the Signal Filter Delay to capture signal conditionally and analyze the Bug further（the Status of the Read is 0X5A, the Command Period of the Read is 10us）. According to the function of the Signal Filter Delay, Zeroplus Logic Analyzer can only capture the 10us Command Period to analyze the Bug when the Data of 0X5A is presented. |
| |
|
|
|
Trigger Page |
| |
| |
Zeroplus Logic Analyzer adds the patent technology of Trigger Page, in other words, the Trigger Page is to page the continuous and long signal data.
Take the set RAM Size as one page, and the position of the trigger point is the first page. After analyzing the data of the first page, users can set the Trigger Page as “2” and restart the Logic Analyzer when the data of the testing board are the same for each time and the setting of the trigger condition is not to be changed; when the Logic Analyzer stops capturing the data and completes the display, the content of the Waveform Display Area is the data of the second page which follows the data of the first page.
For example: The RAM Size is set as 32K; the Sampling Frequency is set as 200MHz; the Trigger Page is “1”. The end point of the captured signal is 147.465us and the former half part of the data is 0X47. When starting to capture with the same RAM Size and Sampling Frequency and setting the Trigger Page as “2”, the start point of the captured data is 147.465us which is the end point of the first page, and users can see the latter part of the data, 0X47. |
| |
|
|
|
Trigger Count |
| |
| |
Zeroplus Logic Analyzer adds the technology of Trigger Count. The Trigger Count function is suitable for this kind of tested signals which have more than one trigger signal according with the Trigger Condition. Users can decide the trigger position where the trigger signal accords with the Trigger Condition. When users want to trigger at the first time when the trigger signal accords with the Trigger Condition, the setting of Trigger Count should be “1” (it is the default); when users want to trigger at the third time when the trigger signal accords with the Trigger Condition, the setting of the Trigger Count should be “3”; the others can follow the former method.
The Max. Trigger Count can be set as “65535”. |
| |
|
|
|
The Analysis Example of Protocol Analyzer - The Decoding of Protocol Analyzer UART |
| |
| |
The Protocol Analyzer UART Analysis Module of Zeroplus Technology can help users to analyze the Protocol Analyzer UART. The packet segments of START, DATA, PARITY CHECK, STOP in signals can be directly displayed on the screen according to the Analysis Module. The Protocol Analyzer UART Analysis Module of Zeroplus Technology provides the function of finding the Baud Rate automatically. Users can activate this function to automatically judge the most suitable Baud Rate for decoding; it can save the time of counting the Baud Rate for users. |
| |
|
|
|
Support LabVIEW |
| |
LabVIEW for LAP-C(16032) Download
How to perform logic analyzer measurement on LabVIEW :
https://www.youtube.com/watch?v=ukK3zUuWszE |
