LAP-C(16064)
  • LAP-C(16064)

    Specifications
     
     
    Sample Rate
      Internal Clock (Timing Mode) 100Hz~200MHz
    External Clock (State Mode) 75MHz
       
     
    Threshold Voltages
      Bandwidth:75MHz
    Working Range: -6V~+6V
    Accuracy: ±0.1V
       
     
    Memory
      Memory:1Mbits
    Depth(Per Channel):64Kbits (Max 16Mbits for compression)
       
     
    Trigger
      Condition: Pattern/Edge
    Trigger Channel : 16 CH
    Post Trigger: YES
    Trigger Level: 1 Level
    Trigger Count: 1~65535
       
     
    Software Functions
      Data Compression : Max 64K bits x 256
    Time Base Range : 5ps~10Ms
    Languages: Chinese (Traditional/Simplified), English, Japanese, Korean, French, German
    Maximum Trigger Page : 8192 Pages
    Waveforrm Data Display
    Filter&Filter Delay
    Trigger Delay
    Unlimited lncreasing Bar
    Automatic Attaching Bar
    Automatic Software Upgrade
    Data Statistic
    Auto-Save
    Filter Bar
    Protocol Analysis
    Protocol Packet List
    File Export
    Data Contrast : Not support
    Latch Function: Not support
    Protocol Analyzer Trigger : parallel
    Pulse Width Trigger Module : option
       
     
    Other
      Power :USB (DC 5V, 500mA)
    Operating System: Windows 2000 / XP(32bits) / Vista / Win 7
    Phase Errors: < 1.5ns
    Maximum Input Voltage: ±30V
    Impedance:500KΩ/10pF
    Safety Certification: FCC / CE / WEEE / RoHS / REACH
       
     
    Extending Channel Capture
      Not support
       
     
    Double Mode
      Not support
       

     

    Electric Specification
     
    Item
    Min
    Typical
    Max
     
    Working Voltage
    DC 4.5V
    DC 5V
    DC 5.5V
     
    Current at Rest
    200mA
     
    Current at Work
    400mA
     
    Power at Rest
    1W
     
    Power at Work
    2W
     
    Error in Phase Off
    - 1.5ns
    + 1.5ns
     
    Vinput of Testing Channels
    - DC30V
    + DC30V
     
    Vreference
    - DC6V
    + DC6V
     
    Impedance
    500KΩ/10pF
     
    Working Temperature
    5 ℃
    70 ℃
     
    Storage Temperature
    -40 ℃
    80 ℃
    • Useful Link

    • Features

      Feature
       
       
      The Buttons on the Logic Analyzer Hardware Own the Function of Sampling:
        There is a START button on the hardware of the Zeroplus Logic Analyzer, and pressing this button can make the Logic Analyzer sample signals when the software of Logic Analyzer is activated. Users can quickly capture data from the testing board by using the START button.
         
       
      Compression
       
        Zeroplus Technology issues the patent technology of Waveform Compression which can capture more waveform data without adding the size of the RAM.
      For example: The RAM Size is set as 1M, and the Sampling Frequency is set as 50MHz. When the Compression function is not activated, Zeroplus Logic Analyzer can only capture waveform data within 20.972ms; when the Compression function is activated, with the same RAM Size (1M) and Sampling Frequency (50MHz), the Logic Analyzer can prolong the waveform data to 3.999s. That is to say, the function of Waveform Compression can improve the amount of the captive data largely.
         
       
      Signal Filter Delay
       
        Zeroplus Technology issues the patent technology of Signal Filter Delay. The function of the Signal Filter Delay can capture the signals conditionally. For example, the Filter Condition of channel A1 is set as High Level; the differences can be seen obviously by the horizontal windows, and the Filter Delay Setup can make the conditions of the Signal Filter more flexible; users can set the time of the Filter Delay as their requirements.



      For example: Clients found Bugs in a group of DUT. The content of the Bug is that a read error may be presented while the program tries to read the data. At that moment, users can use the function of the Signal Filter Delay to capture signal conditionally and analyze the Bug further(the Status of the Read is 0X5A, the Command Period of the Read is 10us). According to the function of the Signal Filter Delay, Zeroplus Logic Analyzer can only capture the 10us Command Period to analyze the Bug when the Data of 0X5A is presented.
         
       
      Trigger Page
       
        Zeroplus Logic Analyzer adds the patent technology of Trigger Page, in other words, the Trigger Page is to page the continuous and long signal data.


      Take the set RAM Size as one page, and the position of the trigger point is the first page. After analyzing the data of the first page, users can set the Trigger Page as “2” and restart the Logic Analyzer when the data of the testing board are the same for each time and the setting of the trigger condition is not to be changed; when the Logic Analyzer stops capturing the data and completes the display, the content of the Waveform Display Area is the data of the second page which follows the data of the first page.


      For example: The RAM Size is set as 32K; the Sampling Frequency is set as 200MHz; the Trigger Page is “1”. The end point of the captured signal is 147.465us and the former half part of the data is 0X47. When starting to capture with the same RAM Size and Sampling Frequency and setting the Trigger Page as “2”, the start point of the captured data is 147.465us which is the end point of the first page, and users can see the latter part of the data, 0X47.
         
       
      Trigger Count
       
        Zeroplus Logic Analyzer adds the technology of Trigger Count. The Trigger Count function is suitable for this kind of tested signals which have more than one trigger signal according with the Trigger Condition. Users can decide the trigger position where the trigger signal accords with the Trigger Condition. When users want to trigger at the first time when the trigger signal accords with the Trigger Condition, the setting of Trigger Count should be “1” (it is the default); when users want to trigger at the third time when the trigger signal accords with the Trigger Condition, the setting of the Trigger Count should be “3”; the others can follow the former method.

      The Max. Trigger Count can be set as “65535”.
         
       
      Chain-Data-Find
        Zeroplus Logic Analyzer adds the function of Chain-Data-Find. The original function of Find Data Value can find only one data , and the function of Chain-Data-Find enhances the Find function; for instance, the signal owns the chain data which are 0X01, 0X02, 0X03…0X25, 0X26, 0X27…0X40, then it can set the 0X25, 0X26 and 0X27 as the target of Find; it improves the efficiency of analyzing the signal.
         
       
      The Analysis Example of Protocol Analyzer - The Decoding of Protocol Analyzer IIC
       
        The Protocol Analyzer IIC Analysis Module of Zeroplus Technology can help users to analyze the Protocol Analyzer IIC. The packet segments of START, ADDRESS, DATA, ACK, NACK, STOP in signals can be directly displayed on the screen according to the Analysis Module. The Protocol Analyzer IIC Analysis Module of Zeroplus Technology provides the function of setting Address and Data Bit as users requirements. It won’t be limited by the special specifications when analyzing the IIC signal; users can set the range from 1bit to 28bit as their requirements.
         
       
      Support LabVIEW
        LabVIEW for LAP-C(16064) Download

      How to logic analyzer measurement on LabVIEW :
      https://www.youtube.com/watch?v=ukK3zUuWszE
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